Good knowledge on Verilog. Language proficiency is expected to be very high.
SV exposure is a value addition.
Good knowledge in circuit design basics
Expert in integrating processor based SOC. Either the target could be ASIC or FPGA.
Exposure to Linting, Formal verification is value addition.
Simulation (RTL, GLS) is must.
18 k -22k + incentives + DA+ HRA extra
if you are interested call